1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof and, more particularly, to a semiconductor device having a fuse and a capacitor at the same level and a method of fabricating the same.
2. Description of the Related Art
A merged memory and logic device, such as a system on chip (SOC) is structured to include memory elements and logic elements together in one semiconductor device. The logic elements typically comprise analog capacitors.
A fuse is widely used in a memory device to provide the memory device with redundancy. The production yield of the memory device can be increased by use of the fuse. With the high integration of a semiconductor device, the height of the semiconductor device is increased. Therefore, a method of forming the fuse on the upper portion of the semiconductor device is widely used in order to facilitate the fusing.
In the meantime, a metal-insulator-metal (MIM) capacitor is widely used as an analog capacitor because its capacitance is easy to control, and its characteristics of the voltage coefficient of capacitance is better than that of a poly Si-insulator-poly Si (PIP) capacitor. Therefore, the merged memory and logic device typically has a fuse and an MIM capacitor together.
FIG. 1 is a sectional view illustrating a conventional MIM capacitor, and a method of fabricating the same. Referring to FIG. 1, the MIM capacitor includes a lower plate 15b placed on a semiconductor substrate 11, an upper plate 19 located above the lower plate, and a capping layer 17 interposed between the lower plate 15b and the upper plate 19. The lower plate 15b is located on the same plane as a lower interconnection line 15a. 
In the meantime, the lower interconnection line 15a is electrically connected to an upper interconnection line 23a passing over the lower interconnection line 15a through a via plug. The upper plate 19 is electrically connected to another upper interconnection line 23b passing over the upper plate 19 through a via plug. The upper interconnection line 23a and the another upper interconnection line 23b are placed in a same plane.
Further, the capping layer 17 may cover the upper surfaces of the lower interconnection line 15a and the lower plate 15b. The capping layer 17 has an opening exposing a predetermined portion of the lower interconnection line 15a such that the lower interconnection line 15a is electrically connected to the upper interconnection line 23a. 
Now, hereinafter, a description is made of a method of fabricating the conventional MIM capacitor. Referring to FIG. 1, a semiconductor substrate 11 is provided. The semiconductor substrate may have discrete devices, such as transistors, and interconnection lines. A lower insulating layer 13 is formed on the semiconductor substrate 11. The lower insulating layer 13 is patterned using a photolithography and etch process to form a line trench and a lower plate trench.
A lower conductive layer is formed on the semiconductor substrate having the trenches. The lower conductive layer may be formed of a copper (Cu) layer. In the case of forming the lower conductive layer as a Cu layer, a Cu diffusion barrier layer and a seed layer are typically formed before the Cu layer is formed. After the lower conductive layer is formed, the lower conductive layer is planarized until the top surface of the lower insulating layer 13 is exposed, to form a lower interconnection line 15a filling the line trench, and a lower plate 15b filling the lower plate trench 15b. 
A capping layer 17 and a plate conductive layer are sequentially formed on the semiconductor substrate having the lower interconnection line 15a and the lower plate 15b. In the case of forming the lower conductive layer as a Cu layer, the capping layer 17 may be formed of a dielectric layer capable of preventing the diffusion of Cu. The plate conductive layer is patterned using a photolithography and etch process to form an upper plate 19 above the lower plate 15b. 
An upper insulating layer 21 is formed on the semiconductor substrate having the upper plate 19. The upper insulating layer 21 and the capping layer 17 are patterned through a photolithography and etch process to form via holes exposing the lower interconnection line 15a and the upper plate 19.
An upper conductive layer is formed on the semiconductor substrate having the via holes, and the upper conductive layer is patterned through a photolithography and etch process. As a result, there is formed an upper interconnection line 23a, which is electrically connected to the lower interconnection line 15a, and there is formed another upper interconnection line 23b, which is electrically connected to the upper plate 19. The upper interconnection lines 23a, 23b may be formed by using a damascene process or a dual damascene process.
The conventional MIM capacitor can be fabricated by forming the lower interconnection line 15a and the lower plate 15b by using a single patterning process, and also by forming the upper interconnection line 23a and the another upper interconnection line 23b by using a single patterning process, which are advantageous.
However, the fabrication of the conventional MIM capacitor requires additional photolithography and etch processes in order to form the upper plate 19. Further, in the case of forming the lower interconnection line 15a and the lower plate 15b using a Cu damascene process, alignment keys are necessary in order to align the upper plate 19 above the lower plate 15b. Therefore, additional photolithography and etch processes are necessary to form the alignment keys. As a result, in order to form the conventional MIM capacitor, there are additionally required photolithography and etch processes for forming the alignment keys, and photolithography and etch processes for forming the upper plate.
A fabrication method of a capacitor without the use of the additional photolithography and etch processes is disclosed in U.S. Pat. No. 6,495,426 (Cheng et al.) entitled “Method for simultaneous formation of integrated capacitor and fuse”. In the method disclosed in U.S. Pat. No. 6,495,426, the fuse and the upper plate are formed using a single photolithography and etch process. Therefore, the additional photolithography and etch processes are not necessary to form the upper plate.
However, in the method disclosed in U.S. Pat. No. 6,495,426, a fuse is formed using a process other than an interconnection line formation process. Therefore, a capping layer interposed between a lower plate and the upper plate should be patterned by using a photolithography and etch process, and a photolithography and etch process for forming the fuse and the upper plate is required.
Accordingly, there are required a semiconductor device fabrication method being capable of forming a fuse and a capacitor while minimizing the photolithography and etch process steps, and a semiconductor device fabricated thereby.